The channel length of metal oxide semiconductor field effect transistors (MOSFETs) is decreasing as the semiconductor device industry continually moves toward smaller devices. Sufficiently small channel lengths result in undesirable characteristics known as short channel effects, including threshold voltage roll-off (Vt-roll-off). Vt roll off with decreasing gate length is a source of variability and limits the process window for complimentary oxide semiconductor (CMOS) technologies. Structures with a laterally non-uniform gate work function are commonly used to alter the Vt-roll-off effect. However, many of the techniques used to make gate-first devices with non-uniform work function gates are not portable to the processes used in making damascene gates.
As opposed to a gate-first device, a gate-last device (also referred to as a replacement gate or damascene gate) is commonly formed by first depositing a high-k gate dielectric on a substrate, depositing polysilicon on the gate dielectric, and patterning the polysilicon into a dummy gate (e.g., a mandrel). Any desired spacers, implants (e.g., source, drain, halo, etc.), silicides, etc., are formed before an interlevel dielectric layer (ILD) is formed over the top of the structure. The ILD is then recessed down to the top of the polysilicon and the polysilicon dummy gate is stripped away, leaving a gate trench in the ILD. Metal is then deposited into the gate trench, resulting in a metal gate formed on a high-k gate dielectric. However, the processing steps involved in forming damascene gates pose unique challenges in the fabrication on a non-uniform (e.g., variable) work function gate.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.